Publications

My ResearchGate profile
My Google Scholar profile







 2019

M. J. Klaiber, D. G. Bailey, S. Simon "Comparative Study and Proof of Single-Pass Connected ComponentsAlgorithms" in Journal of Mathematical Imaging and Vision, June 2019.


 2018


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"Aross the Stack Opportunities for Deep Learning Acceleration" in
Proceedings of the International Symposium on Low Power Electronics and Design, pp. 35


B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky, N. Cao, C.‐Y. Chen, P. Chuang, T.Fox, G. Gristede, M. Guillorn, H.  Haynie, M. Klaiber, D. Lee, S.Lo, G. Maier, M. Scheuermann, S. Venkataramani, C. Vezyrtzis, N. Wang, F. Yee, C. Zhou, P.‐F. Lu, B. Curran, L. Chang, K. Gopalakrishnan "A Scalable Multi‐TeraOPS Deep Learning Processor Core for AI Training and Inference" in 2018 Symposia on VLSI Technology and Circuit,

Blog entry discussion the Multi‐TeraOPS Deep Learning Processor Core
IEEE Spectrum Article discussing the Multi‐TeraOPS Deep Learning Processor Core 

 

2017

M. J. Klaiber "A Parallel and Resource-Efficient Single Lookup Connected Components Analysis Architecture for Reconfigurable Hardware"  Dissertation, University of Stuttgart, 2017.


2016

Michael J. Klaiber, Donald G. Bailey, Sven Simon, "A single-cycle parallel multi-slice connected components analysis hardware architecture" in Springer Journal of Real-Time Image Processing, pp 1–11.


 

2015

Michael J. Klaiber, Donald G. Bailey, Yousef O. Baroud and Sven Simon,  "A Resource-Efficient Hardware Architecture for Connected Components Analysis" in IEEE Transactions on Circuits and Systems for Video Technology.

 

2014

Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey and Sven Simon,  "Adaptive Dynamic On-Chip Memory Management for FPGA-based Reconfigurable Architectures" in 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, Sept. 2014.


2013


Michael J. Klaiber, Donald G. Bailey, Silvia Ahmed, Yousef Baroud, Sven Simon, "A High-Throughput FPGA Architecture for Parallel Connected Components Analysis Based on Label Reuse" in 2013 International Conference on Field-Programmable Technology (FPT), Kyoto, Japan, Dec. 2013.


Donald G. Bailey, Michael J. Klaiber, "Efficient Hardware Calculation of Running Statistics" in Image and Vision Computing New Zealand 2013, Wellington, New Zealand, Nov. 2013.


2012


Michael J. Klaiber, Lars Rockstroh, Zhe Wang, Yousef Baroud and Sven Simon
"A memory-efficient parallel single pass architecture for connected component labeling of streamed images" in 2012 International Conference on Field-Programmable Technology (FPT), pages 159-165, Seoul, Korea, Dec. 2012.